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 MC74LVX4066
Quad Analog Switch/ Multiplexer/Demultiplexer
High-Performance Silicon-Gate CMOS
The MC74LVX4066 utilizes silicon-gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF-channel leakage current. This bilateral switch/multiplexer/demultiplexer controls analog and digital voltages that may vary across the full power-supply range (from VCC to GND). The LVX4066 is identical in pinout to the metal-gate CMOS MC14066 and the high-speed CMOS HC4066A. Each device has four independent switches. The device has been designed so that the ON resistances (RON) are much more linear over input voltage than RON of metal-gate CMOS analog switches. The ON/OFF control inputs are compatible with standard CMOS outputs; with pull-up resistors, they are compatible with LSTTL outputs.
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14-LEAD SOIC D SUFFIX CASE 751A
14-LEAD TSSOP DT SUFFIX CASE 948G
* * * * * * * * *
Fast Switching and Propagation Speeds High ON/OFF Output Voltage Ratio Low Crosstalk Between Switches Diode Protection on All Inputs/Outputs Wide Power-Supply Voltage Range (VCC - GND) = 2.0 to 6.0 Volts Analog Input Voltage Range (VCC - GND) = 2.0 to 6.0 Volts Improved Linearity and Lower ON Resistance over Input Voltage than the MC14016 or MC14066 Low Noise Chip Complexity: 44 FETs or 11 Equivalent Gates
LOGIC DIAGRAM
XA A ON/OFF CONTROL XB B ON/OFF CONTROL XC C ON/OFF CONTROL XD D ON/OFF CONTROL 1 13 4 5 8 6 11 12 10 9 3 2 YA
PIN CONNECTION AND MARKING DIAGRAM (Top View)
XA YA YB XB B ON/OFF CONTROL C ON/OFF CONTROL GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC A ON/OFF CONTROL D ON/OFF CONTROL XD YD YC XC
For detailed package marking information, see the Marking Diagram section on page 10 of this data sheet.
FUNCTION TABLE
On/Off Control Input YB ANALOG OUTPUTS/INPUTS YC L H State of Analog Switch Off On
ORDERING INFORMATION
Device YD MC74LVX4066D ANALOG INPUTS/OUTPUTS = XA, XB, XC, XD PIN 14 = VCC PIN 7 = GND MC74LVX4066DR2 MC74LVX4066DT MC74LVX4066DTR2 SOIC SOIC TSSOP TSSOP 55 Units/Rail 2500 Units/Reel 96 Units/Rail 2500 Units/Reel Package Shipping
(c) Semiconductor Components Industries, LLC, 1999
1
March, 2000 - Rev. 2
Publication Order Number: MC74LVX4066/D
MC74LVX4066
IIIIIIIIIIIIIIIIIIIII I II I I I I I IIIIIIIIIIIII II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I II I I I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I II I I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIII I II I I I II I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I
III II I IIIIIIIIIIIIIIIIIIIIIII II I III II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII II I III II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII
MAXIMUM RATINGS*
Symbol VCC VIS Vin Iin Is Parameter Value Unit V V V Positive DC Supply Voltage (Referenced to GND) Analog Input Voltage (Referenced to GND) Digital Input Voltage (Referenced to GND) - 0.5 to + 7.0 - 0.5 to VCC + 0.5 - 0.5 to VCC + 0.5 20 20 500 450 DC Current Into or Out of ON/OFF Control Pins DC Current Into or Out of Switch Pins Power Dissipation in Still Air, Storage Temperature mA mA PD SOIC Package TSSOP Package mW Tstg TL - 65 to + 150 260
_C _C
Lead Temperature, 1 mm from Case for 10 Seconds
*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- SOIC Package: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open. I/O pins must be connected to a properly terminated line or bus.
v
v
IIII I I I I IIIIIIIIIIIIIIIIIIIII IIII I I IIIIIIIIIIIIIIIIIIIIIII II I IIII I I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I I
Symbol VCC VIS Vin TA Parameter Min 2.0 Max 6.0 Unit V V V V Positive DC Supply Voltage (Referenced to GND) Analog Input Voltage (Referenced to GND) Digital Input Voltage (Referenced to GND) Static or Dynamic Voltage Across Switch GND GND -- VCC VCC 1.2 + 85 100 20 VIO* tr, tf Operating Temperature, All Package Types - 55 0 0
RECOMMENDED OPERATING CONDITIONS
_C
Input Rise and Fall Time, ON/OFF Control Inputs (Figure 10) VCC = 3.3 V 0.3 V VCC = 5.0 V 0.5 V
ns/V
*For voltage drops across the switch greater than 1.2 V (switch on), excessive VCC current may be drawn; i.e., the current out of the switch may contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded.
DC ELECTRICAL CHARACTERISTIC Digital Section (Voltages Referenced to GND)
VCC V 2.0 3.0 4.5 5.5 2.0 3.0 4.5 5.5
Guaranteed Limit
Symbol VIH
Parameter
Test Conditions
- 55 to 25_C 1.5 2.1 3.15 3.85 0.5 0.9 1.35 1.65
v 85_C v 125_C
1.5 2.1 3.15 3.85 0.5 0.9 1.35 1.65 1.5 2.1 3.15 3.85 0.5 0.9 1.35 1.65
Unit V
Minimum High-Level Voltage ON/OFF Control Inputs (Note 1)
Ron = Per Spec
VIL
Maximum Low-Level Voltage ON/OFF Control Inputs (Note 1)
Ron = Per Spec
V
Iin
Maximum Input Leakage Current ON/OFF Control Inputs Maximum Quiescent Supply Current (per Package)
Vin = VCC or GND Vin = VCC or GND VIO = 0 V
5.5V 5.5
0.1 4.0
1.0 40
1.0 160
A A
ICC
1. Specifications are for design target only. Not final specification limits.
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IIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I II I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II II I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I II I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I II I I I II I I II I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIII I II I I I II I IIIIIIIIIIIII III I I I I II II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I I I I II I I I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I II I I II I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I III I I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I
At supply voltage (VCC) approaching 2 V the analog switch-on resistance becomes extremely non-linear. Therefore, for low-voltage operation, it is recommended that these devices only be used to control digital signals (See Figure 1a).
* Used to determine the no-load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC .
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, ON/OFF Control Inputs: tr = tf = 6 ns)
DC ELECTRICAL CHARACTERISTICS Analog Section (Voltages Referenced to GND)
Symbol
Symbol
Ron
tPLH, tPHL
tPZL, tPZH
tPLZ, tPHZ
Ron
CPD
Ion
Ioff
C
Maximum On-Channel Leakage Current, Any One Channel
Maximum Off-Channel Leakage Current, Any One Channel
Maximum Difference in "ON" Resistance Between Any Two Channels in the Same Package
Maximum "ON" Resistance
Power Dissipation Capacitance (Per Switch) (Figure 13)*
Maximum Capacitance
Maximum Propagation Delay, ON/OFF Control to Analog Output (Figures 10 and 1 1)
Maximum Propagation Delay, ON/OFF Control to Analog Output (Figures 10 and 11)
Maximum Propagation Delay, Analog Input to Analog Output (Figures 8 and 9)
Parameter
Parameter
Vin = VIH VIS = 1/2 (VCC - GND) IS 2.0 mA
Vin = VIH VIS = VCC or GND (Figure 4)
Vin = VIL VIO = VCC or GND Switch Off (Figure 3)
Vin = VIH VIS = VCC or GND (Endpoints) |IS| 10 mA (Figures 1, 2)
Vin = VIH VIS = VCC to GND |IS| 10 mA (Figures 1, 2)
v
v
v
Test Conditions
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ON/OFF Control Input
MC74LVX4066
Control Input = GND Analog I/O Feedthrough
3 VCC V VCC V 2.0 3.0 4.5 5.5 2.0 3.0 4.5 5.5 2.0 3.0 4.5 5.5 2.0 3.0 4.5 5.5 5.5 5.5 3.0 4.5 5.5 2.0 3.0 4.5 5.5 -- -- -- - 55 to 25_C - 55 to 25_C Typical @ 25C, VCC = 5.0 V 4.0 3.0 1.0 1.0 0.1 0.1 35 1.0 20 12 8.0 8.0 10 30 20 15 15 15 10 10 -- 30 25 20 -- 40 25 20 Guaranteed Limit Guaranteed Limit 6.0 5.0 2.0 2.0 0.5 0.5 35 1.0 -- 35 30 25 -- 45 30 25 10 25 14 10 10 35 25 18 18 20 12 12 8.0 6.0 2.0 2.0 1.0 1.0 35 1.0 10 30 15 12 12 40 30 22 20 25 15 15 -- 40 35 30 -- 50 35 30
v 85_C v 125_C
v 85_C v 125_C
15
Unit
Unit
A
A
pF
pF ns ns ns
MC74LVX4066
ADDITIONAL APPLICATION CHARACTERISTICS (Voltages Referenced to GND Unless Noted)
III I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I II I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I II I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II II I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIII I II I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I III I I I II I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
Symbol BW Parameter Test Conditions VCC V 4.5 5.5 Limit* 25_C 150 160 Unit Maximum On-Channel Bandwidth or Minimum Frequency Response (Figure 5) fin = 1 MHz Sine Wave Adjust fin Voltage to Obtain 0 dBm at VOS Increase fin Frequency Until dB Meter Reads - 3 dB RL = 50 , CL = 10 pF MHz -- Off-Channel Feedthrough Isolation (Figure 6) fin Sine Wave Adjust fin Voltage to Obtain 0 dBm at VIS fin = 10 kHz, RL = 600 , CL = 50 pF
4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5
- 50 - 50 - 37 - 37 100 200
dB
fin = 1.0 MHz, RL = 50 , CL = 10 pF
--
Feedthrough Noise, Control to Switch (Figure 7)
Vin 1 MHz Square Wave (tr = tf = 6 ns) Adjust RL at Setup so that IS = 0 A RL = 600 , CL = 50 pF RL = 10 k, CL = 10 pF
v
mVPP
--
Crosstalk Between Any Two Switches (Figure 12)
fin Sine Wave Adjust fin Voltage to Obtain 0 dBm at VIS fin = 10 kHz, RL = 600 , CL = 50 pF
50 100
- 70 - 70 - 80 - 80
dB
fin = 1.0 MHz, RL = 50 , CL = 10 pF
THD
Total Harmonic Distortion (Figure 14)
fin = 1 kHz, RL = 10 k, CL = 50 pF THD = THDMeasured - THDSource VIS = 4.0 VPP sine wave VIS = 5.0 VPP sine wave
%
4.5 5.5
0.10 0.06
*Guaranteed limits not tested. Determined by design and verified by qualification.
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MC74LVX4066
250 Is = 1mA 400 350 300 25C Ron (Ohms) 150 Is = 5mA Is = 9mA 50 50 0 Is = 15mA 0 0.5 1 Vin (Volts) 1.5 2 2.5 0 0 0.5 1 Vin (Volts) 1.5 2 2.5 Ron (Ohms) 250 200 150 100 85C 125C -55C
200
100
Figure 1a. Typical On Resistance, VCC = 2.0 V, T = 25C
Figure 1b. Typical On Resistance, VCC = 2.0 V
35 30 25 Ron (Ohms) Ron (Ohms) 20 15 10 5 0 0 1 2 Vin (Volts) 3 4
20 18 16 14 12 10 8 6 4 2 0 0 1 2 Vin (Volts) 3 4 5 125C 85C 25C -55C 125C 85C 25C -55C
Figure 1c. Typical On Resistance, VCC = 3.0 V
Figure 1d. Typical On Resistance, VCC = 4.5 V
18 16 14 12 Ron (Ohms) 10 8 6 4 2 0 0 1 2 3 Vin (Volts) 4 5 6 GND ANALOG IN 125C 85C 25C -55C PLOTTER
PROGRAMMABLE POWER SUPPLY - +
MINI COMPUTER
DC ANALYZER
VCC DEVICE UNDER TEST COMMON OUT
Figure 1e. Typical On Resistance, VCC = 5.5 V
Figure 2. On Resistance Test Set-Up
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MC74LVX4066
VCC VCC GND VCC A OFF 14 VCC A GND ON 14 N/C VCC
7
SELECTED CONTROL INPUT
VIL 7
SELECTED CONTROL INPUT
VIH
Figure 3. Maximum Off Channel Leakage Current, Any One Channel, Test Set-Up
Figure 4. Maximum On Channel Leakage Current, Test Set-Up
VCC 14 fin 0.1F ON
VOS fin 0.1F
VIS OFF RL SELECTED CONTROL INPUT 7
VCC 14
VOS
CL*
dB METER
CL*
dB METER
7
SELECTED CONTROL INPUT
VCC
*Includes all probe and jig capacitance.
*Includes all probe and jig capacitance.
Figure 5. Maximum On-Channel Bandwidth Test Set-Up
Figure 6. Off-Channel Feedthrough Isolation, Test Set-Up
VCC/2 14 RL OFF/ON
VCC
VCC/2
RL IS
VOS CL* VCC ANALOG IN tPLH 50% ANALOG OUT 50% GND tPHL
VCC GND
Vin 1 MHz tr = tf = 3 ns CONTROL
7
SELECTED CONTROL INPUT
*Includes all probe and jig capacitance.
Figure 7. Feedthrough Noise, ON/OFF Control to Analog Out, Test Set-Up
Figure 8. Propagation Delays, Analog In to Analog Out
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MC74LVX4066
VCC 14 ANALOG IN ON CL* 50% ANALOG OUT 50% *Includes all probe and jig capacitance. tPZH tPHZ 90% VOH HIGH IMPEDANCE ANALOG OUT TEST POINT CONTROL 90% 50% 10% tPZL tPLZ tr tf VCC GND HIGH IMPEDANCE 10% VOL
7
SELECTED CONTROL INPUT
VCC
Figure 9. Propagation Delay Test Set-Up
Figure 10. Propagation Delay, ON/OFF Control to Analog Out
VIS VCC RL 14 ON 0.1 F TEST POINT OFF VCC OR GND RL SELECTED CONTROL INPUT 7 VCC/2 RL CL* RL CL* fin VOS
POSITION 1 WHEN TESTING tPHZ AND tPZH 1 2 VCC 1 2 ON/OFF CL* SELECTED CONTROL INPUT 7 POSITION 2 WHEN TESTING tPLZ AND tPZL VCC 14 1 k
VCC/2
VCC/2
*Includes all probe and jig capacitance.
*Includes all probe and jig capacitance.
Figure 11. Propagation Delay Test Set-Up
Figure 12. Crosstalk Between Any Two Switches, Test Set-Up
VCC A 14 N/C OFF/ON N/C 0.1 F fin ON RL SELECTED CONTROL INPUT VCC/2 7 SELECTED CONTROL INPUT VCC CL* VIS
VCC
VOS TO DISTORTION METER
7
ON/OFF CONTROL *Includes all probe and jig capacitance.
Figure 13. Power Dissipation Capacitance Test Set-Up
Figure 14. Total Harmonic Distortion, Test Set-Up
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MC74LVX4066
0 - 10 - 20 - 30 dBm - 40 - 50 - 60 - 70 - 80 - 90 1.0 2.0 FREQUENCY (kHz) 3.0 DEVICE SOURCE FUNDAMENTAL FREQUENCY
Figure 15. Plot, Harmonic Distortion
APPLICATION INFORMATION The ON/OFF Control pins should be at VCC or GND logic levels, VCC being recognized as logic high and GND being recognized as a logic low. Unused analog inputs/outputs may be left floating (not connected). However, it is advisable to tie unused analog inputs and outputs to VCC or GND through a low value resistor. This minimizes crosstalk and feedthrough noise that may be picked-up by the unused I/O pins. The maximum analog voltage swings are determined by the supply voltages VCC and GND. The positive peak analog voltage should not exceed VCC. Similarly, the negative peak analog voltage should not go below GND. In the example below, the difference between VCC and GND is six volts. Therefore, using the configuration in Figure 16, a maximum analog signal of six volts peak-to-peak can be controlled. When voltage transients above VCC and/or below GND are anticipated on the analog channels, external diodes (Dx) are recommended as shown in Figure 17. These diodes should be small signal, fast turn-on types able to absorb the maximum anticipated current surges during clipping. An alternate method would be to replace the Dx diodes with Mosorbs (MosorbTM is an acronym for high current surge protectors). Mosorbs are fast turn-on devices ideally suited for precise DC protection with no inherent wear out mechanism.
VCC = 6.0 V + 6.0 V 0V 14 ANALOG I/O ON ANALOG O/I + 6.0 V 0V Dx
VCC 16 ON Dx VCC SELECTED CONTROL INPUT 7
VCC Dx
Dx
SELECTED CONTROL INPUT 7
OTHER CONTROL INPUTS (VCC OR GND)
OTHER CONTROL INPUTS (VCC OR GND)
Figure 16. 6.0 V Application
Figure 17. Transient Suppressor Application
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MC74LVX4066
+5 V +5 V
ANALOG SIGNALS R* LSTTL/ NMOS R* R* R* 5 6 14 15 R* = 2 TO 10 k
14
ANALOG SIGNALS
ANALOG SIGNALS
14
ANALOG SIGNALS
LVX4066
CONTROL INPUTS 7
LSTTL/ NMOS/ ABT/ ALS
LVXT4066 5 6 14 15 CONTROL INPUTS 7
a. Using Pull-Up Resistors
b. Using LVXT4066 Figure 18. LSTTL/NMOS to CMOS Interface
VDD = 5 V
VCC = 2.0 TO 7.0 V
13 3 5 7 9 11 14
1
16
ANALOG SIGNALS
14
ANALOG SIGNALS
LVX4066 MC14504 2 4 6 8 10 5 6 14 15 CONTROL INPUTS 7
Figure 19. TTL/NMOS-to-CMOS Level Converter Analog Signal Peak-to-Peak Greater than 5 V
CHANNEL 4
1 OF 4 SWITCHES 1 OF 4 SWITCHES COMMON I/O 1 OF 4 SWITCHES 1 OF 4 SWITCHES - INPUT 1 OF 4 SWITCHES + 0.01 F 1 2 34 CONTROL INPUTS LF356 OR EQUIVALENT OUTPUT
CHANNEL 3
CHANNEL 2
CHANNEL 1
Figure 20. 4-Input Multiplexer
Figure 21. Sample/Hold Amplifier
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MC74LVX4066
MARKING DIAGRAMS (Top View)
14
13
12
11
10
9
8
14
13
12
11
10
9
8
LVX4066 AWLYWW*
1 2 3 4 5 6 7 1 2 3
LVX 4066 ALYW*
4 5 6 7
14-LEAD SOIC D SUFFIX CASE 751A
14-LEAD TSSOP DT SUFFIX CASE 948G
*See Applications Note #AND8004/D for date code and traceability information.
PACKAGE DIMENSIONS
D SUFFIX PLASTIC SOIC PACKAGE CASE 751A-03 ISSUE F
-A-
14 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
-B-
1 7
P 7 PL
0.25 (0.010)
M
B
M
G C
R X 45
F
SEATING PLANE
D 14 PL 0.25 (0.010)
M
K TB
S
M A
S
J
DIM A B C D F G J K M P R
MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0 7 5.80 6.20 0.25 0.50
INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.228 0.244 0.010 0.019
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MC74LVX4066
PACKAGE DIMENSIONS
DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948G-01 ISSUE O
14X K REF NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
N
2X
L/2
14
8
0.25 (0.010) M
L
PIN 1 IDENT. 1 7
B -U-
N F DETAIL E K K1 J J1
0.15 (0.006) T U
S
A -V-
C 0.10 (0.004) -T- SEATING
PLANE
D
G
H
DETAIL E
http://onsemi.com
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EEE CCC EEE CCC
SECTION N-N -W-
MC74LVX4066
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
NORTH AMERICA Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: ONlit@hibbertco.com Fax Response Line: 303-675-2167 or 800-344-3810 Toll Free USA/Canada N. American Technical Support: 800-282-9855 Toll Free USA/Canada EUROPE: LDC for ON Semiconductor - European Support German Phone: (+1) 303-308-7140 (M-F 1:00pm to 5:00pm Munich Time) Email: ONlit-german@hibbertco.com French Phone: (+1) 303-308-7141 (M-F 1:00pm to 5:00pm Toulouse Time) Email: ONlit-french@hibbertco.com English Phone: (+1) 303-308-7142 (M-F 12:00pm to 5:00pm UK Time) Email: ONlit@hibbertco.com EUROPEAN TOLL-FREE ACCESS*: 00-800-4422-3781 *Available from Germany, France, Italy, England, Ireland CENTRAL/SOUTH AMERICA: Spanish Phone: 303-308-7143 (Mon-Fri 8:00am to 5:00pm MST) Email: ONlit-spanish@hibbertco.com ASIA/PACIFIC: LDC for ON Semiconductor - Asia Support Phone: 303-675-2121 (Tue-Fri 9:00am to 1:00pm, Hong Kong Time) Toll Free from Hong Kong & Singapore: 001-800-4422-3781 Email: ONlit-asia@hibbertco.com JAPAN: ON Semiconductor, Japan Customer Focus Center 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan 141-8549 Phone: 81-3-5740-2745 Email: r14525@onsemi.com ON Semiconductor Website: http://onsemi.com
For additional information, please contact your local Sales Representative.
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MC74LVX4066/D


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